CMOS Based Design Simulation Of Adder /Subtractor Using Different Foundries
نویسندگان
چکیده
-In this paper a 4 bit parallel adder/subtractor circuit has been designed and analyzed. The circuit uses a controlled adder/subtractor circuit which converts the negative numbers into their 2’s complement. A comparative study of the silicon area and the power consumption has been done in the circuit using different channel lengths such as 65nm, 45nm. The circuit is designed and simulated using DSCH schematic tool and the layout is developed by Microwind VLSI CAD Tool. The designed circuit has shown a remarkable reduction in the consumed power of 93% and a reduction of 49% in consumed area in 45nm foundry as compared to 65nm foundry. The simulation has been done using BSIM4 device modeling.
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